XA7Z020-1CLG400Q_汽车级 Zynq-7000 SoC
The XA Zynq™-7000 Automotive family is based on the Xilinx® SoC architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device
  • 2.5 DMIPS/MHz per CPU
  • CPU frequency: Up to 667 MHz
  • 256 KB on-chip RAM (OCM)
  • 16-bit or 32-bit interfaces to DDR3L, DDR3, DDR2, or LPDDR2 memories
详细内容


XA Zynq-7000 SoC First Generation Architecture

The XA Zynq™-7000 Automotive family is based on the Xilinx®SoC architecture.These products integrate a feature-rich dual-core ARM®Cortex™-A9 based processing system(PS)and 28 nm Xilinx programmable logic(PL)in a single device.The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory,external memory interfaces,and a rich set of peripheral connectivity interfaces.This highly integrated,flexible,and power-optimized solution is ideal for high computationally intensive and performance demanding applications.The automotive family focuses on automotive applications and consists of the Z-7010,Z-7020,and Z-7030 devices.

Processing System(PS)

Dual-Core ARM Cortex-A9 Based

Application Processor Unit(APU)

•2.5 DMIPS/MHz per CPU

•CPU frequency:Up to 667 MHz

•Coherent multiprocessor support

•ARMv7-A architecture

•TrustZone security

•Thumb-2 instruction set

•Jazelle RCT execution Environment Architecture

•NEON media-processing engine

•Single and double precision Vector Floating Point Unit(VFPU)

•CoreSight™technology and Program Trace

Macrocell(PTM)

•Timer and Interrupts

•Three watchdog timers

•One global timer

•Two triple-timer counters

Caches

•32 KB Level 1 4-way set-associative instruction

and data caches(independent for each CPU)

•512 KB 8-way set-associative Level 2 cache

(shared between the CPUs)

•Byte-parity support

On-Chip Memory

•On-chip boot ROM

•256 KB on-chip RAM(OCM)

•Byte-parity support

External Memory Interfaces

•Multiprotocol dynamic memory controller

•16-bit or 32-bit interfaces to DDR3L,DDR3,

DDR2,or LPDDR2 memories

•ECC support in 16-bit mode

•1 GB of address space using single rank of 8-,

16-,or 32-bit-wide memories

•Static memory interfaces